Wafer bonding is becoming increasingly popular for coupling elements on different wafers before singulation (dicing). A wafer of 4″-8″ diameter may contain hundreds or thousands of devices, and the bonding of two wafers can replace the conventional bonding of each of these hundreds or thousands of devices individually.
In the conventional fabrication of light emitting devices (LEDs), for example, a wafer containing the semiconductor devices is diced, and the individual devices are subsequently bonded to a submount that provides structural support and means for coupling to external power sources or other circuitry. Generally, the submount is sized to facilitate subsequent manufacturing processes, such as mounting on a printed circuit board, or placement in a fixture. If the size of the LED is substantially smaller than the size of the submount, this process is fairly efficient.
However, particularly in the field of LEDs, the size of the individual device (chip) has been increasing, due, for example, to an increase in the area of the light emitting element, or for the inclusion of multiple light emitting elements in a single device. Accordingly, chip-scale packaging, wherein the overall size of the packaged (mounted) device is not significantly larger than the chip, is becoming quite common. In such cases, wherein the size of the chip is similar to the size of the submount, bonding a wafer of LEDs to a wafer of submounts may provide for a very efficient manufacturing process.
Often, the materials used for the different wafers are of different materials, the material of one wafer being chosen to facilitate the fabrication of the semiconductor devices, and the material of the other wafer being chosen to facilitate structurally and electrically sound packaging. In the example of light emitting devices, the semiconductor wafer often contains a thick layer of GaN-based or GaP material, such as AlInGaN, AlInGaP, InGaN, etc., on a sapphire growth substrate, whereas the submount wafer may typically include one or more metal layers on a silicon substrate.
Because different materials are commonly used for forming semiconductors and forming submounts, the feasibility of wafer-bonding is subject to a number of challenges. Differences in the coefficient of thermal expansion (CTE) between the two wafers, or other layers of the combination, may lead to warpage after assembly, particularly when relatively high temperatures are used to effect the bonding. In addition to problems caused during the bonding process, the resultant warped packages will introduce problems in subsequent processes, such as processes used to remove layers, texture surfaces, and so on, and may result in reliability problems when these warped packages are mounted to printed circuit boards or other fixtures.
Conventionally, one method of reducing warpage is to assure that one of the bonded materials is substantially thinner than the other material, the thicker material enforcing a certain flatness. However, in the case of semiconductor packaging, the grown substrate and the submount substrate are typically of comparable thicknesses. The growth substrate must be thick enough to support the fabrication process, and the submount substrate must be thick enough to provide structural support to the finished package.